Here is our last lab day for the project. The entire VHDL code is finished after several times of modification. The task for this week is to test the hardware (FPGA board).
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| Ready to use |
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| Insert 10p |
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| Insert 20p |
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| Insert 50p |
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| Insert 1Pound |
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| Select item 'C' |
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| Collect change |
Here is the work that members have done on our fifth lab day.
Ye Zhu
I arranged files as a part of preparation for bench inspection. Apart from this, I collected and updated blogs for our group. Since there is a deadline for blog submission, I wrote the summary of the blog as the description shown on the Y2 project website, Xiaotian Zhang helped me with the summary.
Junlin Guo
Because we started the test on DE2 board, I was in charge of the simulation of coin_returner and help others to debug. Besides, I took some photo for our poster.
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